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Conference Paper: Direct Virtual Memory Access from FPGA for High-Productivity Heterogeneous Computing

TitleDirect Virtual Memory Access from FPGA for High-Productivity Heterogeneous Computing
Authors
Issue Date2013
PublisherI E E E Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290
Citation
International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, 9-11 December 2013. In I E E E International Conference on FieId-Programmable Technology Proceedings, 2013, p. 458-461, article no. 6718414 How to Cite?
AbstractHeterogeneous computing utilizing both CPU and FPGA requires access to data in the main memory from both devices. While a typical system relies on software executing on the CPU to orchestrate all data movements between the FPGA and the main memory, our demo presents a complementary FPGA-centric approach that allows gateware to directly access the virtual memory space as part of the executing process without involving the CPU. A caching address translation buffer was implemented alongside the user FPGA gateware to provide runtime mapping between virtual and physical memory addresses. The system was implemented on a commercial off-the-shelf FPGA add-on card to demonstrate the viability of such approach in low-cost systems. Experiment demonstrated reasonable performance improvement when compared to a typical software-centric implementation; while the number of context switches between FPGA and CPU in both kernel and user mode was significantly reduced, freeing the CPU for other concurrent user tasks. © 2013 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/201235
ISBN

 

DC FieldValueLanguage
dc.contributor.authorNg, HCen_US
dc.contributor.authorChoi, YMen_US
dc.contributor.authorSo, HKHen_US
dc.date.accessioned2014-08-21T07:18:19Z-
dc.date.available2014-08-21T07:18:19Z-
dc.date.issued2013en_US
dc.identifier.citationInternational Conference on Field-Programmable Technology (FPT), Kyoto, Japan, 9-11 December 2013. In I E E E International Conference on FieId-Programmable Technology Proceedings, 2013, p. 458-461, article no. 6718414en_US
dc.identifier.isbn9781479921997-
dc.identifier.urihttp://hdl.handle.net/10722/201235-
dc.description.abstractHeterogeneous computing utilizing both CPU and FPGA requires access to data in the main memory from both devices. While a typical system relies on software executing on the CPU to orchestrate all data movements between the FPGA and the main memory, our demo presents a complementary FPGA-centric approach that allows gateware to directly access the virtual memory space as part of the executing process without involving the CPU. A caching address translation buffer was implemented alongside the user FPGA gateware to provide runtime mapping between virtual and physical memory addresses. The system was implemented on a commercial off-the-shelf FPGA add-on card to demonstrate the viability of such approach in low-cost systems. Experiment demonstrated reasonable performance improvement when compared to a typical software-centric implementation; while the number of context switches between FPGA and CPU in both kernel and user mode was significantly reduced, freeing the CPU for other concurrent user tasks. © 2013 IEEE.en_US
dc.languageengen_US
dc.publisherI E E E Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290en_US
dc.relation.ispartofI E E E International Conference on FieId-Programmable Technology Proceedingsen_US
dc.rightsI E E E International Conference on FieId-Programmable Technology Proceedings. Copyright © I E E E Computer Society.en_US
dc.rights©2013 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleDirect Virtual Memory Access from FPGA for High-Productivity Heterogeneous Computingen_US
dc.typeConference_Paperen_US
dc.identifier.emailSo, HKH: hso@eee.hku.hken_US
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FPT.2013.6718414en_US
dc.identifier.scopuseid_2-s2.0-84894133431-
dc.identifier.hkuros234175en_US
dc.identifier.spage458, article no. 6718414en_US
dc.identifier.epage461, article no. 6718414en_US
dc.publisher.placeUnited States-

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