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postgraduate thesis: Efficiency enhancement for nanoelectronic transport simulations

TitleEfficiency enhancement for nanoelectronic transport simulations
Authors
Advisors
Issue Date2013
PublisherThe University of Hong Kong (Pokfulam, Hong Kong)
Citation
Huang, J. [黃俊]. (2013). Efficiency enhancement for nanoelectronic transport simulations. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153685
AbstractContinual technology innovations make it possible to fabricate electronic devices on the order of 10nm. In this nanoscale regime, quantum physics becomes critically important, like energy quantization effects of the narrow channel and the leakage currents due to tunneling. It has also been utilized to build novel devices, such as the band-to-band tunneling field-effect transistors (FETs). Therefore, it presages accurate quantum transport simulations, which not only allow quantitative understanding of the device performances but also provide physical insight and guidelines for device optimizations. However, quantum transport simulations usually require solving repeatedly the Green’s function or the wave function of the whole device region with open boundary treatment, which are computationally cumbersome. Moreover, to overcome the short-channel effects, modern devices usually employ multi-gate structures that are three-dimensional, making the computation very challenging. It is the major target of this thesis to enhance the simulation efficiency by proposing several fast numerical algorithms. The other target is to apply these algorithms to study the physics and performances of some emerging electronic devices. First, an efficient method is implemented for real space simulations with the effective mass approximation. Based on the wave function approach, asymptotic waveform evaluation combined with a complex frequency hopping algorithm is successfully adopted to characterize electron conduction over a wide energy range. Good accuracy and efficiency are demonstrated by simulating several n-type multi-gate silicon FETs. This technique is valid for arbitrary potential distribution and device geometry, making it a powerful tool for studying n-type silicon nanowire (SiNW) FETs in the presence of charged impurity and surface roughness scattering. Second, a model order reduction (MOR) method is proposed for multiband simulation of nanowire structures. Employing three- or six-band k.p Hamiltonian, the non-equilibrium Green’s function (NEGF) equations are projected into a much smaller subspace constructed by sampling the Bloch modes of each cross-section layer. Together with special sampling schemes and Krylov subspace methods for solving the eigenmodes, large cross-section p-type SiNW FETs can be simulated. A novel device, junctionless FET, is then investigated. It is found that its doping density, channel orientation, and channel size need to be carefully optimized in order to outperform the classical inversion-mode FET. With a spurious band elimination process, the MOR method is subsequently extended to the eight-band k.p model, allowing simulation of band-to-band tunneling devices. In particular, tunneling FETs with indium arsenide (InAs) nanowire channel are studied, considering different channel orientations and configurations with source pockets. Results suggest that source pocket has no significant impact on the performances of the nanowire device due to its good electrostatic integrity. At last, improvements are made for open boundary treatment in atomistic simulations. The trick is to condense the Hamiltonian matrix of the periodic leads before calculating the surface Green’s function. It is very useful for treating leads with long unit cells.
DegreeDoctor of Philosophy
SubjectNanoelectronics - Mathematical methods
Dept/ProgramElectrical and Electronic Engineering
Persistent Identifierhttp://hdl.handle.net/10722/196031

 

DC FieldValueLanguage
dc.contributor.advisorChew, WC-
dc.contributor.advisorChen, G-
dc.contributor.advisorJiang, L-
dc.contributor.authorHuang, Jun-
dc.contributor.author黃俊-
dc.date.accessioned2014-03-21T03:50:06Z-
dc.date.available2014-03-21T03:50:06Z-
dc.date.issued2013-
dc.identifier.citationHuang, J. [黃俊]. (2013). Efficiency enhancement for nanoelectronic transport simulations. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153685-
dc.identifier.urihttp://hdl.handle.net/10722/196031-
dc.description.abstractContinual technology innovations make it possible to fabricate electronic devices on the order of 10nm. In this nanoscale regime, quantum physics becomes critically important, like energy quantization effects of the narrow channel and the leakage currents due to tunneling. It has also been utilized to build novel devices, such as the band-to-band tunneling field-effect transistors (FETs). Therefore, it presages accurate quantum transport simulations, which not only allow quantitative understanding of the device performances but also provide physical insight and guidelines for device optimizations. However, quantum transport simulations usually require solving repeatedly the Green’s function or the wave function of the whole device region with open boundary treatment, which are computationally cumbersome. Moreover, to overcome the short-channel effects, modern devices usually employ multi-gate structures that are three-dimensional, making the computation very challenging. It is the major target of this thesis to enhance the simulation efficiency by proposing several fast numerical algorithms. The other target is to apply these algorithms to study the physics and performances of some emerging electronic devices. First, an efficient method is implemented for real space simulations with the effective mass approximation. Based on the wave function approach, asymptotic waveform evaluation combined with a complex frequency hopping algorithm is successfully adopted to characterize electron conduction over a wide energy range. Good accuracy and efficiency are demonstrated by simulating several n-type multi-gate silicon FETs. This technique is valid for arbitrary potential distribution and device geometry, making it a powerful tool for studying n-type silicon nanowire (SiNW) FETs in the presence of charged impurity and surface roughness scattering. Second, a model order reduction (MOR) method is proposed for multiband simulation of nanowire structures. Employing three- or six-band k.p Hamiltonian, the non-equilibrium Green’s function (NEGF) equations are projected into a much smaller subspace constructed by sampling the Bloch modes of each cross-section layer. Together with special sampling schemes and Krylov subspace methods for solving the eigenmodes, large cross-section p-type SiNW FETs can be simulated. A novel device, junctionless FET, is then investigated. It is found that its doping density, channel orientation, and channel size need to be carefully optimized in order to outperform the classical inversion-mode FET. With a spurious band elimination process, the MOR method is subsequently extended to the eight-band k.p model, allowing simulation of band-to-band tunneling devices. In particular, tunneling FETs with indium arsenide (InAs) nanowire channel are studied, considering different channel orientations and configurations with source pockets. Results suggest that source pocket has no significant impact on the performances of the nanowire device due to its good electrostatic integrity. At last, improvements are made for open boundary treatment in atomistic simulations. The trick is to condense the Hamiltonian matrix of the periodic leads before calculating the surface Green’s function. It is very useful for treating leads with long unit cells.-
dc.languageeng-
dc.publisherThe University of Hong Kong (Pokfulam, Hong Kong)-
dc.relation.ispartofHKU Theses Online (HKUTO)-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsThe author retains all proprietary rights, (such as patent rights) and the right to use in future works.-
dc.subject.lcshNanoelectronics - Mathematical methods-
dc.titleEfficiency enhancement for nanoelectronic transport simulations-
dc.typePG_Thesis-
dc.identifier.hkulb5153685-
dc.description.thesisnameDoctor of Philosophy-
dc.description.thesislevelDoctoral-
dc.description.thesisdisciplineElectrical and Electronic Engineering-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.5353/th_b5153685-

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