ResearcherPage View Count

Geo Map
AS - Asia2513
NA - North America1867
EU - Europe1383
HKU - The University of Hong Kong276
AF - Africa35
OC - Oceania16
SA - South America5
UND - Undefined39
US - United States1729
CN - China1549
IE - Ireland389
KR - Republic of Korea356
GB - United Kingdom328
HKU - The University of Hong Kong276
HK - Hong Kong252
NL - Netherlands231
FR - France190
SG - Singapore156
OTH - Others678
The University of Hong Kong276
Central District92
Design of quadruple precision multiplier architectures with SIMD single and double precision support13
High-throughput time-stretch imaging flow cytometry for multi-class classification of phytoplankton24
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform38
Performance-driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems36
Extending BORPH for shared memory reconfigurable computers46
Architecture for quadruple precision floating point division with multi-precision support63
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH104
Radio Testbeds using BEE293
A Real-time Coprime Line Scan Super-resolution System for Ultra-fast Microscopy25
A model for peak matrix performance on FPGAs71
PACoGen: A Hardware Posit Arithmetic Core Generator12
Computational Light Field Generation Using Deep Nonparametric Bayesian Learning11
An Introduction to BORPH: BEE2 and ROACH15
Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy62
High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing18
An integrated debugging environment for reprogrammble hardware systems93
Design space exploration for sparse matrix-matrix multiplication on FPGAs113
On IIR-based bit-stream multipliers147
Reducing dynamic power consumption in FPGAs using precomputation110
An Integer Linear Programming Model for Automated Matrix Operation Scheduling on FPGAs65
Dual-mode double precision division architecture33
Architecture for dual-mode quadruple precision floating point adder60
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels66
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation87
Computational image speckle suppression using block matching and machine learning11
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay38
Design space exploration for sparse matrix-matrix multiplication on FPGAs127
Large-scale multi-class image-based cell classification with deep learning20
File system access from reconfigurable FPGA hardware processes in borph105
Operating System for Re-Programmable Heterogeneous Multiprocessor Hardware7
Quantitative phase imaging flow cytometry for ultra-large-scale single-cell biophysical phenotyping22
Automatic system architecture synthesis for FPGA-based reconfigurable computers72
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs25
A soft processor overlay with tightly-coupled FPGA accelerator53
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division79
UE-TCAM: an ultra efficient SRAM-based TCAM59
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System21
All-passive pixel super-resolution of time-stretch imaging77
Quad-level bit-stream signal processing on FPGAs88
Architecture Generator for Type-3 Unum Posit Adder/Subtractor51
Operation scheduling for FPGA-based reconfigurable computers81
Medical ultrasound imaging: To GPU or not to GPU?145
Computational single-cell classification using deep learning on bright-field and phase images47
BORPH: operating system support on the NetFPGA platform80
Wastewater treatment in Myanmar: A multidisciplinary learning experience for engineering and science students from two countries37
Taylor series based architecture for Quadruple Precision Floating Point Division55
A model for matrix multiplication performance on FPGAs83
Sparse hierarchical nonparametric Bayesian Learning for light field representation and denoising44
Direct sigma-delta modulated signal processing in FPGA90
Scheduling mixed-architecture processes in tightly coupled FPGA-CPU reconfigurable computers45
A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization20
Teaching introductory electrical engineering: project-based learning experience131
Real-time GPU-based adaptive beamformer for high quality ultrasound imaging88
Energy-Efficient Dataflow Computations on FPGAs using Application-Specific Coarse-Grain Architecture Synthesis49
A comparison of SAR image speckle filters267
Ultra-large-scale single-cell Quantitative Phase Imaging14
Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process97
Multi‐ATOM: Ultrahigh‐throughput single‐cell quantitative phase imaging with subcellular resolution97
Dual-Mode Double Precision / Two-Parallel Single Precision Floating Point Multiplier Architecture56
Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU53
ASIC design and verification in an FPGA environment136
Zero-configuration identity-based signcryption scheme for Smart Grid260
Urban Farming in Myanmar: An Experiential Learning Project for Engineering and Science Students from Hong Kong and Myanmar29
Towards FPGA-assisted spark: An SVM training acceleration case study51
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging80
Improving usability of FPGA-based reconfigurable computers through operating system support84
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division45
The First 25 Years of the FPL Conference - Significant Papers48
Map-reduce processing of K-means algorithm with FPGA-accelerated computer cluster96
A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency76
Fringe Pattern Improvement and Super-Resolution Using Deep Learning in Digital Holography18
Ultrafast label-free imaging cytometry enables massive and in-depth single-cell biophysical phenotyping16
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory45
PARC: ultrafast and accurate clustering of phenotypic data of millions of single cells19
Deep convolutional neural network for single-cell image analysis27
Power-delay and energy-delay tradeoffs in sparse matrix-matrix multiplication on FPGAs84
Data-driven light field depth estimation using deep convolution neural network92
GraVF: a vertex-centric distributed graph processing framework on FPGAs53
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH116
Universal number posit arithmetic generator on FPGA54
DSP48E efficient floating point multiplier architectures on FPGA69
Towards Flexible Automatic Generation of Graph Processing Gateware15
Zero-configuration identity-based IP network encryptor103
FPGA Overlays83
Significant papers from the First 25 Years of the FPL Conference71
Configurable Architectures For Multi-mode Floating Point Adders52
Unsupervised tracking with a low computational cost using the doubly stochastic Dirichlet process mixture model35
QuickDough: a rapid FPGA loop accelerator design framework using soft CGRA overlay102
Direct Virtual Memory Access from FPGA for High-Productivity Heterogeneous Computing52
Runtime filesystem support for reconfigurable FPGA hardware processes in BORPH77
Mixed-architecture process scheduling on tightly coupled reconfigurable computers35